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12-bit, 80 msps/105 msps adc ad9432 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2009 analog devices, inc. all rights reserved. features on-chip reference and track-and-hold on-chip input buffer power dissipation: 850 mw typical at 105 msps 500 mhz analog bandwidth snr: 67 db @ 49 mhz ain at 105 msps sfdr: 80 db @ 49 mhz ain at 105 msps 2.0 v p-p analog input range 5.0 v supply operation 3.3 v cmos/ttl outputs twos complement output format applications communications base stations and zero-if subsystems wireless local loop (wll) local multipoint distribution service (lmds) hdtv broadcast cameras and film scanners general introduction the ad9432 is a 12-bit, monolithic sampling analog-to-digital converter (adc) with an on-chip track-and-hold circuit and is optimized for high speed conversion and ease of use. the prod- uct operates up to a 105 msps conversion rate with outstanding dynamic performance over its full operating range. the adc requires only a single 5.0 v power supply and a 105 mhz encode clock for full performance operation. no external refer- ence or driver components are required for many applications. the digital outputs are ttl-/cmos-compatible, and a separate output power supply pin supports interfacing with 3.3 v logic. the encode input supports either differential or single-ended mode and is ttl-/cmos-compatible. fabricated on an advanced bicmos process, the ad9432 is available in a 52-lead low profile quad flat package (lqfp) and in a 52-lead thin quad flat package (tqfp_ep). the ad9432 is specified over the industrial temperature range of ?40c to +85c. functional block diagram 12 12 t/h buf pipeline adc ref timing output staging ad9432 v cc v dd gnd vrefout vrefin d11 to d0 or encode encode ain ain 00587-001 figure 1.
ad9432 rev. f | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general introduction ....................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing diagram ........................................................................... 5 ? absolute maximum ratings ............................................................ 6 ? explanation of test levels ........................................................... 6 ? thermal characteristics .............................................................. 6 ? esd caution .................................................................................. 6 ? pin configurations and function descriptions ........................... 7 ? typical performance characteristics ............................................. 8 ? terminology .................................................................................... 11 ? equivalent circuits ......................................................................... 12 ? theory of operation ...................................................................... 13 ? analog input ............................................................................... 13 ? encode input ............................................................................... 13 ? encode voltage level definition .............................................. 13 ? digital outputs ........................................................................... 14 ? voltage reference ....................................................................... 14 ? timing ......................................................................................... 14 ? applications information .............................................................. 15 ? using the ad8138 to drive the ad9432 ................................ 15 ? outline dimensions ....................................................................... 16 ? ordering guide .......................................................................... 16 ? revision history 6/09rev. e to rev. f updated format .................................................................. universal reorganized layout ............................................................ universal added tqfp_ep package ................................................. universal deleted lqfp_ed package ............................................... universal changes to thermal characteristics section ................................ 6 changes to pin configurations and function descriptions section ................................................................................................ 7 changes to terminology section.................................................. 11 deleted evaluation board section ................................................ 15 updated outline dimensions ....................................................... 16 changes to ordering guide .......................................................... 16 1/02rev. d to rev. e edits to specifications ....................................................................... 3 edits to absolute maximum ratings .............................................. 4 edits to ordering guide ................................................................... 4 addition of text to using the ad9432 section .......................... 10 edits to figure 17a .......................................................................... 15 edits to figure 17b ......................................................................... 16 addition of sq-52 package outline ............................................. 18
ad9432 rev. f | page 3 of 16 specifications v dd = 3.3 v, v cc = 5.0 v; external reference; differential encode input, unless otherwise noted. table 1. parameter temp test 80 msps 105 msps level min typ max min typ max unit resolution 12 12 bits dc accuracy differential nonlinearity (dnl) 25c i ?0.75 0.25 +0.75 ?0.75 0.25 +0.75 lsb full vi ?1.0 0.5 +1.0 ?1.0 0.5 +1.0 lsb integral nonlinearity (inl) 25c i ?1 .0 0.5 +1.0 ?1.0 0.5 +1.0 lsb full vi ?1.5 1.0 +1.5 ?1.5 1.0 +1.5 lsb no missing codes full vi guaranteed guaranteed gain error 1 25c i ?5 +2 +7 ?5 +2 +7 % fs gain tempco 1 full v 150 150 ppm/c analog inputs (ain, ain ) input voltage range full v 2 2 v p-p common-mode voltage full v 3.0 3.0 v input offset voltage full vi ?5 0 +5 ?5 0 +5 mv input resistance full vi 2 3 4 2 3 4 k input capacitance 25c v 4 4 pf analog bandwidth, full power 25c v 500 500 mhz analog reference output voltage full vi 2.4 2.5 2.6 2.4 2.5 2.6 v tempco full v 50 50 ppm/c input bias current full vi 15 50 15 50 ? switching performance maximum conversion rate full vi 80 105 msps minimum conversion rate full iv 1 1 msps encode pulse width high (t eh ) 25c iv 4.0 6.2 4.0 4.8 ns encode pulse width low (t el ) 25c iv 4.0 6.2 4.0 4.8 ns aperture delay (t a ) 25c v 2.0 2.0 ns aperture uncertainty (jitter) 25c v 0.25 0.25 ps rms output valid time (t v ) 2 full vi 3.0 5.3 3.0 5.3 ns output propagation delay (t pd ) 2 full vi 5.5 8.0 5.5 8.0 ns output rise time (t r ) 2 full v 2.1 2.1 ns output fall time (t f ) 2 full v 1.9 1.9 ns out-of-range recovery time 25c v 2 2 ns transient response time 25c v 2 2 ns latency full iv 10 10 cycles digital inputs encode input common mode full v 1.6 1.6 v differential input (encode, encode ) full v 750 750 mv single-ended input logic 1 voltage full iv 2.0 2.0 v logic 0 voltage full iv 0.8 0.8 v input resistance full vi 3 5 8 3 5 8 k input capacitance 25c v 4.5 4.5 pf digital outputs logic 1 voltage (v dd = 3.3 v) full vi v dd ? 0.05 v dd ? 0.05 v logic 0 voltage (v dd = 3.3 v) full vi 0.05 0.05 v output coding twos comp lement twos complement
ad9432 rev. f | page 4 of 16 parameter temp test 80 msps 105 msps level min typ max min typ max unit power supply power dissipation 3 full vi 790 1000 850 1100 mw i vcc full vi 158 200 170 220 ma i vdd full vi 9.5 12.2 12.5 16 ma power supply rejection ratio (psrr) 25c i ?5 +0.5 +5 ?5 +0.5 +5 mv/v dynamic performance 4 signal-to-noise ratio (snr) (without harmonics) f in = 10 mhz 25c i 65.5 67.5 65.5 67.5 db f in = 40 mhz 25c i 65 67.2 67.2 db f in = 49 mhz 25c i 67.0 64 67.0 db f in = 70 mhz 25c v 66.1 66.1 db signal-to-noise and distortion (sinad) ratio (with harmonics) f in = 10 mhz 25c i 65 67.2 65 67.2 db f in = 40 mhz 25c i 64.5 66.9 66.9 db f in = 49 mhz 25c i 66.7 63 66.7 db f in = 70 mhz 25c v 65.8 65.8 db effective number of bits (enob) f in = 10 mhz 25c v 11.0 11.0 bits f in = 40 mhz 25c v 10.9 10.9 bits f in = 49 mhz 25c v 10.9 10.9 bits f in = 70 mhz 25c v 10.7 10.7 bits second-order and third-order harmonic distortion f in = 10 mhz 25c i ?75 ?85 ?75 ?85 dbc f in = 40 mhz 25c i ?73 ?85 ?83 dbc f in = 49 mhz 25c i ?83 ?72 ?80 dbc f in = 70 mhz 25c v ?80 ?78 dbc worst other harmonic or spur (excluding second-order and third-order harmonics) f in = 10 mhz 25c i ?80 ?90 ?80 ?90 dbc f in = 40 mhz 25c i ?80 ?90 ?90 dbc f in = 49 mhz 25c i ?90 ?80 ?90 dbc f in = 70 mhz 25c v ?90 ?90 dbc two-tone intermodulation distortion (imd) f in1 = 29.3 mhz; f in2 = 30.3 mhz 25c v ?75 ?75 dbc f in1 = 70.3 mhz; f in2 = 71.3 mhz 25c v ?66 ?66 dbc 1 gain error and gain temperature coefficients are based on the adc only (with a fixed 2.5 v external reference and a 2 v p-p di fferential analog input). 2 t v and t pd are measured from the transition points of the encode input to the 50%/50% levels of the digital output swing. the digital out put load during testing is not to exceed an ac load of 10 pf or a dc current of 4 0 a. rise and fall times are measured from 10% to 90%. 3 power dissipation measured with encode at rated speed and a dc analog input (outputs static, i vdd = 0). 4 snr/harmonics based on an analog input voltage of C0.5 dbfs referenced to a 2 v full-scale input range.
ad9432 rev. f | page 5 of 16 timing diagram t v t pd t el t eh t a 1/ f s sample n ? 1 sample n + 1 data n ? 11 data n ? 10 data n ? 1 data n data n + 1 data n ? 9 data n ? 2 sample n + 9 sample n + 10 sample n + 11 sample n ain d11 to d0 encode encode 00587-003 figure 2. timing diagram
ad9432 rev. f | page 6 of 16 absolute maximum ratings thermal characteristics table 2. parameter rating v dd 6 v v cc 6 v analog inputs ?0.5 v to v cc + 0.5 v digital inputs ?0.5 v to v dd + 0.5 v vrefin ?0.5 v to v cc + 0.5 v digital output current 20 ma operating temperature range ?55c to +125c storage temperature range ?65c to +150c maximum junction temperature 150c maximum case temperature 150c table 3 lists ad9432 thermal characteristics for simulated typical performance in a 4-layer jedec board, horizontal orientation. table 3. thermal resistance package type ja jma jc unit 52-lead lqfp (st-52) no airflow 50 c/w 52-lead tqfp_ep (sv-52-2) 1 2 c/w no airflow 19.3 c/w 1.0 m/s airflow 16 c/w 1 bottom of package (soldered exposed pad). stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution explanation of test levels i 100% production tested. ii 100% production tested at 25c and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi 100% production tested at 25c; guaranteed by design and characterization testing for industrial temperature range.
ad9432 rev. f | page 7 of 16 pin configurations and function descriptions 52 v cc 51 gnd 50 ain 49 ain 48 gnd 47 v cc 46 vrefou t 45 vrefin 44 v cc 43 gnd 42 v cc 41 dnc 40 gnd 38 gnd 37 v cc 36 v cc 33 gnd 34 gnd 35 gnd 39 gnd 32 v dd 31 dgnd 30 d0 (lsb) 28 d2 27 d3 29 d1 2 v cc 3 gnd 4 gnd 7 encode 6 v cc 5 v cc 1 gnd 8 encode 9 gnd 10 v cc 12 dgnd 13 v dd 11 gnd notes 1. dnc = do not conne c t. 14 or 15 d11 (msb) 16 d10 17 d9 18 d8 19 d7 20 d6 21 dgnd 22 v dd 23 v dd 24 dgnd 25 d5 26 d4 pin 1 ad9432 top view (not to scale) 00587-002 00587-044 pin 1 ad9432 top view (not to scale) 1 gnd 2 v cc 3 gnd 4 gnd 5 v cc 6 v cc 7 encode 8 encode 9 gnd 10 v cc 11 gnd 12 dgnd 13 v dd 14 or 15 d11 (msb) 16 d10 17 d9 18 d8 19 d7 20 d6 21 dgnd 22 v dd 23 v dd 24 dgnd 25 d5 26 d4 40 gnd 41 dnc 42 v cc 43 gnd 44 v cc 45 vrefin 46 vrefout 47 v cc 48 gnd 49 ain 50 ain 51 gnd 52 v cc 27 d3 28 d2 29 d1 30 d0 (lsb) 31 dgnd 32 v dd 33 gnd 34 gnd 35 gnd 36 v cc 37 v cc 38 gnd 39 gnd notes 1. although not required in all applications, the exposed paddle on the underside of the package should be soldered to the ground plane. soldering the exposed paddle to the pcb increases the reliability of the solder joints, maximizing the thermal capability of the package. figure 3. pin configuration, lqfp fi gure 4. pin configuration, tqfp_ep table 4. pin function descriptions pin no. mnemonic description 1, 3, 4, 9, 11, 33, 34, 35, 38, 39, 40, 43, 48, 51 gnd analog ground. 2, 5, 6, 10, 36, 37, 42, 44, 47, 52 v cc analog supply (5 v). 7 encode encode clock for adc, complementary. 8 encode encode clock for adc, true. adc samples on rising edge of encode. 12, 21, 24, 31 dgnd digital output ground. 13, 22, 23, 32 v dd digital output power supply (2.7 v to 3.6 v). 14 or out-of-range output. 15 to 20, 25 to 30 d11 to d6, d5 to d0 digital output. 41 dnc do not connect. 45 vrefin reference input for adc (2.5 v typical). bypass with 0.1 f capacitor to ground. 46 vrefout internal reference output (2.5 v typical). 49 ain analog input, true. 50 ain analog input, complementary. exposed pad (tqfp_ep) although not required in all applications, the exposed paddle on the underside of the tqfp_ep package should be soldered to the ground plane. soldering the exposed paddle to the pcb increases the reliability of the solder joints, ma ximizing the thermal capability of the package.
ad9432 rev. f | page 8 of 16 typical performance characteristics 90 60 70 65 85 80 75 snr/sinad/sfdr (db) encode (msps) 0 20 40 80 100 120 140 160 60 ain = 10.3mhz sinad sfdr snr 00587-009 figure 5. snr/sinad/sfdr vs. f s , f in = 10.3 mhz harmonics (dbc) encode (msps) 0 20 40 80 100 120 140 160 60 00587-010 ?90 ?95 ?100 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 2nd 3rd ain = 10.3mhz figure 6. second-order and third-order harmonics vs. f s , f in = 10.3 mhz sinad (db) analog input frequency (mhz) 0 20 40 80 100 120 140 200 160 180 60 00587-011 70 65 60 55 50 45 40 encode = 105msps sinad (?3.0dbfs) sinad (?6.0dbfs) sinad (?0.5dbfs) figure 7. sinad vs. f in , f s = 105 msps snr (db) analog input frequency (mhz) 0 50 100 150 250 200 00587-012 70 65 60 55 50 ain = ?0.5dbfs figure 8. snr vs. f in , encode = 105 msps harmonics (dbc) analog input frequency (mhz) 0 20 40 80 100 120 140 200 160 180 60 00587-013 100 90 80 70 60 50 40 encode = 105msps 2nd or 3rd (?0.5dbfs) 2nd or 3rd (?3.0dbfs) 2nd or 3rd (?6.0dbfs) figure 9. second-order and third-order harmonics vs. f in , f s = 105 msps worst other (dbc) analog input frequency (mhz) 0 20 40 80 100 120 140 200 160 180 60 00587-014 100 90 80 70 60 50 40 encode = 105msps worst other (?0.5dbfs) worst other (?6.0dbfs) worst other (?3.0dbfs) figure 10. worst other (excluding second-order and third-order harmonics) vs. f in , f s = 105 msps
ad9432 rev. f | page 9 of 16 amplitude (dbfs) frequency 00587-015 0 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 encode = 105msps ain = 10.3mhz (?0.53dbfs) snr = 67.32db sinad = 67.07db sfdr = ?85dbc figure 11. fft: f s = 105 msps, f in = 10.3 mhz amplitude (dbfs) frequency 00587-016 0 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 encode = 105msps ain = 27.0mhz (?0.52dbfs) snr = 67.3db sinad = 67.0db sfdr = ?83.1dbc figure 12. fft: f s = 105 msps, f in = 27 mhz amplitude (dbfs) frequency 00587-017 0 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 encode = 105msps ain = 40.9mhz (?0.56dbfs) snr = 67.2db sinad = 66.9db sfdr = ?80dbc figure 13. fft: f s = 105 msps, f in = 40.9 mhz amplitude (dbfs) frequency 00587-018 0 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 encode = 105msps ain = 50.3mhz (?0.46dbfs) snr = 67.0db sinad = 66.7db sfdr = ?80dbc figure 14. fft: f s = 105 msps, f in = 50.3 mhz amplitude (dbfs) frequency 00587-019 0 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 ain1 = 29.3mhz (?7dbfs) ain2 = 30.3mhz (?7dbfs) encode = 105msps figure 15. two-tone fft, wideband: f s = 105 msps, ain1 = 29.3 mhz, ain2 = 30.3 mhz amplitude (dbfs) frequency 00587-020 0 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 ain1 = 70.3mhz (?7dbfs) ain2 = 71.3mhz (?7dbfs) encode = 105msps figure 16. two-tone fft, wideband: f s = 105 msps, ain1 = 70.3 mhz, ain2 = 71.3 mhz
ad9432 rev. f | page 10 of 16 worst-case spurious (dbc and dbfs) analog input power level (dbfs) ?80 ?70 ?50 ?40 ?30 0 ?20 ?10 ?60 00587-021 110 90 100 70 80 50 60 40 10 20 30 0 encode = 105msps ain = 50.3mhz dbfs dbc figure 17. single-tone sfdr, f s = 105 msps, f in = 50.3 mhz dnl (lsb) 00587-022 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 figure 18. differential nonlinearity, f s = 105 msps inl (lsb) 00587-023 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 figure 19. integral nonlinearity, f s = 105 msps voltage (v) current (ma) 02 68 4 00587-024 3.0 2.5 2.0 1.5 1 0 figure 20. voltage reference output vs. current load
ad9432 rev. f | page 11 of 16 terminology analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between a differential crossing of encode and encode and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential nonlinearity (dnl) the deviation of any code from an ideal 1 lsb step. effective number of bits (enob) the effective number of bits (enob) is calculated from the measured snr based on the following equation: 02.6 log20db76.1 ? ? ? ? ? ? ? ? ? +? = amplitude input amplitude scalefull snr enob measured encode pulse width/duty cycle pulse width high is the minimum amount of time that the encode pulse should be left in the logic 1 state to achieve the rated per- formance. pulse width low is the minimum amount of time that the encode pulse should be left in the logic 0 state. at a given clock rate, these specifications define an acceptable encode duty cycle. harmonic distortion the ratio of the rms signal amplitude fundamental frequency to the rms signal amplitude of a single harmonic component (second, third, and so on); reported in dbc. integral nonlinearity (inl) the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least square curve fit. maximum conversion rate the maximum encode rate at which parametric testing is performed. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. output propagation delay the delay between a differential crossing of encode and encode and the time when all output data bits are within valid logic levels. power supply rejection ratio (psrr) the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise and distortion (sinad) ratio the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. signal-to-noise ratio (snr) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral com- ponents, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious compo- nent may or may not be a harmonic. may be reported in dbc (degrades as signal level is lowered) or in dbfs (always related back to converter full scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone (f 1 , f 2 ) to the rms value of the worst third-order intermodulation product; reported in dbc. products are located at 2f 1 ? f 2 and 2f 2 ? f 1 . two-tone sfdr the ratio of the rms value of either input tone (f 1 , f 2 ) to the rms value of the peak spurious component. the peak spurious com- ponent may or may not be an imd product. may be reported in dbc (degrades as signal level is lowered) or in dbfs (always related back to converter full scale). worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second-order and third-order harmonic); reported in dbc.
ad9432 rev. f | page 12 of 16 equivalent circuits v cc vrefin 00587-004 figure 21. voltage reference input circuit v cc vrefout 00587-005 figure 22. voltage reference output circuit 00587-006 100 ? 100 ? 8k? 8k? 17k ? 17k ? v cc encode encode figure 23. encode input circuit v dd dx 00587-007 figure 24. digital output circuit 00587-008 5k ? 7k ? 5k? 7k? v cc a in a in figure 25. analog input circuit
ad9432 rev. f | page 13 of 16 theory of operation the ad9432 is a 12-bit pipeline converter that uses a switched- capacitor architecture. optimized for high speed, this converter provides flat dynamic performance up to frequencies near nyquist. dnl transitional errors are calibrated at final test to a typical accuracy of 0.25 lsb or less. analog input the analog input to the ad9432 is a differential buffer. the input buffer is self-biased by an on-chip resistor divider that sets the dc common-mode voltage to a nominal 3 v (see the equivalent circuits section). rated performance is achieved by driving the input differentially. the minimum input offset voltage is obtained when driving from a source with a low differential source impedance, such as a transformer in ac applications. capacitive coupling at the inputs increases the input offset voltage by as much as 25 mv. driving the adc single-ended degrades performance. for best dynamic perfor- mance, impedances at ain and ain should match. special care was taken in the design of the analog input section of the ad9432 to prevent damage and corruption of data when the input is overdriven. the nominal input range is 2 v p-p. each analog input is 1 v p-p when driven differentially. 00587-025 4 .0 3.5 2.5 3.0 2.0 ain ain figure 26. full-scale analog input range encode input any high speed adc is extremely sensitive to the quality of the sampling clock provided by the user. a track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the adc output. for this reason, considerable care has been taken in the design of the encode input of the ad9432, and the user is advised to give commensurate thought to the clock source. the encode input supports differential or single-ended mode and is fully ttl-/cmos-compatible. note that the encode inputs cannot be driven directly from pecl level signals (v ihd is 3.5 v maximum). pecl level signals can easily be accommodated by ac coupling, as shown in figure 27 . good performance is obtained using an mc10el16 translator in the circuit to drive the encode inputs. 00587-026 pecl gate encode ad9432 encode 510 ? 0.1f 0.1f 510? figure 27. ac coupling to encode inputs encode voltage level definition the voltage level definitions for driving encode and encode in single-ended and differential mode are shown in . figure 28 0 0587-027 v ihd v icm v id v ild encode encode v ihs v ils encode 0.1f figure 28. differential and single-ended input levels table 5. encode inputs input min nominal max differential signal amplitude (v id ) 500 mv 750 mv high differential input voltage (v ihd ) 3.5 v low differential input voltage (v ild ) 0 v common-mode input (v icm ) 1.25 v 1.6 v high single-ended voltage (v ihs ) 2 v 3.5 v low single-ended voltage (v ils ) 0 v 0.8 v often, the cleanest clock source is a crystal oscillator producing a pure sine wave. in this configuration, or with any roughly symmet- rical clock input, the input can be ac-coupled and biased to a reference voltage that also provides the encode. this ensures that the reference voltage is centered on the encode signal.
ad9432 rev. f | page 14 of 16 digital outputs the digital outputs are 3.3 v (2.7 v to 3.6 v) ttl-/cmos- compatible for lower power consumption. the output data format is twos complement (see table 6 ). table 6. twos complement output coding (v ref = 2.5 v) code ain ? ain (v) digital output +2047 1.000 0111 1111 1111 0 0 0000 0000 0000 ?1 ?0.00049 1111 1111 1111 ?2048 ?1.000 1000 0000 0000 the out-of-range (or) output is logic low for normal operation. during any clock cycle when the adc output data (dx) reaches positive or negative full scale (+2047 or ?2048), the or output goes high. the or output is internally generated each clock cycle. it has the same pipeline latency and propagation delay as the adc output data and remains high until the output data reflects an in-range condition. the adc output bits (dx) do not roll over and, therefore, remain at positive or negative full scale (+2047 or ?2048) while the or output is high. voltage reference a stable and accurate 2.5 v voltage reference is built into the ad9432 (vrefout). in normal operation, the internal refer- ence is used by strapping pin 45 to pin 46 and placing a 0.1 f decoupling capacitor at vrefin. the input range can be adjusted by varying the reference voltage applied to the ad9432. no appreciable degradation in performance occurs when the reference is adjusted 5%. the full-scale range of the adc tracks reference voltage changes linearly. timing the ad9432 provides latched data outputs, with 10 pipeline delays. data outputs are included or available one propagation delay (t pd ) after the rising edge of the encode command (see figure 2 ). the length of the output data lines and the loads placed on them should be minimized to reduce transients within the ad9432; these transients can detract from the dynamic performance of the converter. the minimum guaranteed conversion rate of the ad9432 is 1 msps. at internal clock rates below 1 msps, dynamic perfor- mance may degrade. therefore, input clock rates below 1 mhz should be avoided. during initial power-up, or whenever the clock to the ad9432 is interrupted, the output data will not be accurate for 200 ns or 10 clock cycles, whichever is longer.
ad9432 rev. f | page 15 of 16 applications information using the ad8138 to drive the ad9432 the ad8138 differential output op amp can be used to drive the ad9432 in dc-coupled applications. the ad8138 was specifically designed for adc driver applications. superior snr performance is maintained up to analog frequencies of 30 mhz. the ad8138 op amp provides single-ended-to-differential conversion, which allows for a low cost alternative to transformer coupling for ac applications, as well. the circuit in figure 29 was breadboarded, and the measured performance is shown in figure 30 and figure 31 . these figures are for 5 v supplies at the ad8138 ; with a single 5 v supply at the ad8138 , performance dropped by about 1 db to 2 db. figure 30 shows snr and sinad for a ?1 dbfs analog input frequency varied from 2 mhz to 40 mhz with an encode rate of 105 msps. the measurements are for nominal conditions at room temperature. figure 31 shows the second-order and third-order harmonic distortion performance under the same conditions. the dc common-mode voltage for the ad8138 outputs can be adjusted via the v ocm input to provide the 3 v common-mode voltage that the ad9432 inputs require. 00587-028 ad8138 ad9432 10pf 0.1f 25? 500? 500 ? 50 ? 50 ? 50 ? 2k? 3k? 5v 500 ? vin ain ain v ocm 10pf 500? 22pf figure 29. ad8138/ad9432 schematic snr/sinad (db) ain (mhz) 02 0 40 00587-029 62 63 64 65 66 61 60 6 0 snr sinad figure 30. measured snr and sinad (encode = 105 msps) harmonics (db) ain (mhz) 02 0 40 00587-030 ?90 ?80 6 0 ? 70 ?100 h2 h3 figure 31. measured second-order an d third-order harmonic distortion (encode = 105 msps)
ad9432 rev. f | page 16 of 16 outline dimensions compliant to jedec standards ms-026-bcc top view (pins down) 40 52 1 14 13 26 27 39 0.65 bsc lead pitch 0.38 0.32 0.22 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.10 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 12.20 12.00 sq 11.80 10.20 10.00 sq 9.80 051706-a figure 32. 52-lead low profile quad flat package [lqfp] (st-52) dimensions shown in millimeters compliant to jedec standards ms-026-acc 40 52 1 14 13 26 27 39 12.00 bsc sq 10.00 bsc sq 1.20 max 0.75 0.60 0.45 view a top view (pins down) pin 1 40 52 14 1 13 26 27 39 0.65 bsc lead pitch 0.38 0.32 0.22 bottom view (pins up) 7.30 bsc sq exposed pad 072508-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. seating plane 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw 0 min 7 3.5 0 0.15 0.05 figure 33. 52-lead thin quad flat package, exposed pad [tqfp_ep] (sv-52-2) dimensions shown in millimeters ordering guide model temperature range packag e description package option ad9432bstz-80 1 ?40c to +85c 52-lead low profile quad flat package [lqfp] st-52 ad9432bstz-105 1 ?40c to +85c 52-lead low profile quad flat package [lqfp] st-52 ad9432bsvz-80 1 ?40c to +85c 52-lead thin quad flat package, exposed pad [tqfp_ep] sv-52-2 ad9432bsvz-105 1 ?40c to +85c 52-lead thin quad flat package, exposed pad [tqfp_ep] sv-52-2 1 z = rohs compliant part. ?2002C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00587-0-6/09(f)

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